Integrated circuits are subject to early failure, also referred to as infant mortality, which is caused by latent defects in the circuits. In particular, semiconductors that have a relatively large die size and use thin oxides are susceptible to infant mortality problems. For quality reasons, circuit manufactures desire to remove these early failure circuits, or die, from the product line prior to shipment to customers. In addition, circuit manufactures desire to remove these early failure die from the product line prior to placement of the die into multi-chip modules (CM) where a single failed die may result in failure and scrapping of the entire MCM.
The bulk of these early failures can be detected prior to shipment of the circuits by exercising the circuits at a high temperature and a working voltage to simulate actual use. Exercising the circuit includes applying power and sending data signals to the circuit to activate various portions of the circuit. For example, in the case of a memory circuit each of the memory cells are exercised by storing and retrieving data from each of the cells. When this exercise process is performed at a high temperature, the process is called burn-in.
The conventional burn-in process is described in several references: Williams, Thomas, Securing Known Good Due, Advanced Packaging, page 50, Fall, 1992; Maliniak, David, Known-Good Die Poised to Take Off, Electronic Design, page 55, Nov. 21, 1994; AEHR Test Systems, Known Good Die—The Total Solution, company brochure, date unknown; Detar, Jim, Intel Launches “SmartDie” Program, Electronic News, May 30, 1994; U.S. Pat. No. 5,047,711, Wafer-Level Burn-In Testing of Integrated Circuits, to Smith et al., issued Sep. 10, 1991; Fee, See-Hack, Known Good Die: A commercial Solution for Burn-in and Test Before Packaging, presented at Semicon Japan, December 1994; Prokopchak, Lina, Development of a Solution for Achieving Known-Good-Die, presented at ITC, Washington, D.C., September 1994; Mayerfield, Pam, Flexibility and Modularity Drive Today's Burn-In/Test Systems, EE-Evaluation Engineering, November 1994; and U.S. Pat. No. 4,968,931, Apparatus and Method for Burning In Integrated Circuit Wafers, to Littlebury et al., issued Nov. 6, 1990.
To begin the conventional burn-in process, the individual die in wafer form are initially tested for minimal functionality for a short time and at ambient temperatures in a probe card station. This initial probe station test is run at a slow speed of approximately 5 MHz or less, due to possible interference problems. The test involves placing probes directly onto the pads of the die and then testing each of the die's components. The test may take approximately five seconds to three minutes per die, in addition to the relocation time of moving the probes from one die to another. Each of the die can be tested individually at the probe station because die in wafer form are not electrically connected to one another. Due to the short time period used to test each die, the die are tested sequentially until each die on the wafer has been classified as either good (pass) or bad (fail).
The good die are cut from the wafer and mounted in a package which is in turn mounted on a burn-in board. The die typically are permanently mounted in the package so that a die which fails final testing after the burn-in exercise will be discarded along with its package. A typical burn-in board includes space for multiple packages electrically connected to one another, for example, fifteen packages per board, so that the die on a single burn-in board can be exercised in parallel. Several burn-in boards are placed in a burn-in oven in an inert atmosphere for an extended period of time and exercised at a high temperature. In one example, 52 boards are exercised in a burn-in oven for 24 hours at a temperature of 125° C. The burn-in exercise is run at a speed of approximately 400 MHz to simulate actual working conditions. After the burn-in process, the die undergo a final test to eliminate those which have failed during burn-in. These failed die are removed from the product line.
Burn-in ovens may have a footprint of twelve square feet or more and may be over five feet tall. Accordingly, entire rooms or floors of fabrication facilities may be devoted to the burn-in process. Due to the long time frame and high temperature of the burn-in process, the energy usage is substantial. The process of placing the individual die in packages, placing the packages on the burn-in board, placing the burn-in boards in the burn-in ovens, and placing the packaged die in the final die tester is labor intensive.
The hardware used during the burn-in process is package specific. In other words, packages and burn-in boards for each specific type of die must be purchased. These costs can be enormous. In the case of multi-chip modules (CM), the package and burn-in board costs can be tenfold over the cost of single die packages and burn-in boards. These package and burn-in board costs continue to rise due to higher pin counts and specifications.
In one example, a wafer includes six hundred die. Each of the die are placed in a one-hundred-and-sixty pin package. Each package may cost $50 or more. The package is placed on a burn-in board that receives thirty-six packages per board and costs approximately $4,000. Seventeen boards are required to burn-in all the die from the single wafer. The cost of seventeen burn-in boards is approximately $68,000. The cost of six hundred packages is approximately $30,000. Moreover, the cost of the oven, energy usage, and labor must be added to these package and burn-in board costs.
Accordingly, manufactures are researching methods to simplify and minimize the cost of the burn-in process. Once method involves providing temporary packages for holding the die during the burn-in process. These temporary packages are expensive and have reliability questions surrounding their use. A substantial labor investment is still required in placing the die in these temporary packages. The energy usage of these temporary packages is generally similar to the requirements of the permanent packages.
A process that would allow wafer level burn-in exercising of individual die would eliminate the cost of packages and packaging labor for bad die, lower the cost of burn-in boards and allow more die to be placed in a single burn-in oven at one time. However, there are multiple obstacles to overcome in exercising die at the wafer level.
Each die has multiple signals that are required to control/exercise the die and multiple devices on each die that must be stimulated. Connection to a single die using electrical probes is common practice, as in the short duration, ambient temperature initial probe test mentioned above. However, the burn-in process takes a long period of time and is conducted at a high temperature and in an inert atmosphere. Accordingly, sequential wafer level burning in of the individual die on a wafer would not be time or cost efficient. If the electrical probe connection method were attempted for simultaneous wafer level burn-in for all die on the wafer, (using the same die example cited above) the probe card would require one-hundred-and-sixty pins times six-hundred die per wafer, or 96,000 probes. Each of these 96,000 probes must be aligned to connect to each of the corresponding die pads, without damaging the pads, to a tolerance of +/−0.001 inch, and must not drift out of this tolerance range during exercising of the circuit. Accordingly, the probes must not bend or bow due to temperature changes ranging from ambient to as much as 140° C. Each of these 96,000 connections must be made within the eight-inch diameter of the wafer. With so many electrical probes concentrated in such a small area, electrical noise and cross talk problems are inevitable. Wafer level burn-in using electrical probe connections does not appear to be feasible.